1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to low power consuming memory sense amplifying circuitry.
2. Description of the Related Art
Read only memory (ROM) devices are generally array structures having a multiplicity of columns and a multiplicity of rows. Although any row and associated column may be addressed in a ROM, only selected row and column intersections may activate a storage transistor. Typically, when an intersection containing a storage transistor is addressed, digital data representing a "0-bit" is read. On the other hand, when an intersection that does not contain a storage transistor is addressed, digital data representing a "1-bit" is read. As is well known in the art, once digital data is addressed within a ROM device, a very small voltage amplitude representing the addressed digital data is sensed. However, to produce a readable voltage amplitude representing useful digital data, a sense amplifier is typically implemented to amplify the sensed digital data which may be a 0-bit or a 1-bit.
FIG. 1A shows a conventional ROM addressing block diagram used for accessing digital data stored within a ROM core 100. By way of example, when ROM core 100 includes 1,000 rows by 1,000 columns, ROM core 100 may be classified as a one megabit (1 MB) ROM storage device. Accordingly, host computers typically access ROM core 100 through an address input bus 110 that may be coupled to a conventional X-DECODER 102 and a conventional Y-DECODER 104. In general, X-DECODER 102 is used for addressing a selected row within ROM core 100, and Y DECODER 102 is used for addressing a selected column within ROM core 100. By way of example, X and Y decoders are generally implemented for reducing memory array aspect ratios by filing (i.e., dividing) long addressable memory columns into several shorter memory columns. Once folded into several columns, the X and Y decoders are capable of accessing the addressed data by appropriately performing a suitable muliplexing function.
Once a row and column is selected from ROM core 100, a very low voltage which may be as low as 20 milli-volts (mV) may be sensed on a data bus 112 representing the addressed data. As described above, to appropriately read the addressed data, suitable amplification is typically performed in a sense amplifier 106. Once the sensed data signal is amplified to about 3.3 volts or about 5 volts in sense amplifier 106, the voltage amplified data (i.e., digital data) is passed through as an amplified data output 114 to an output buffer 108. At output buffer 108, the voltage amplified data is current amplified to provide an appropriate level of current drive once the read data is passed to a ROM output bus 116.
FIG. 1B illustrates a conventional single ended differential pair sense amplifier 106. As shown, sense amplifier 106 includes a rail voltage (Vcc) which is typically about 3.3 volts or 5 volts connected to a transistor 122 and a transistor 120 that form a well known current mirror. Connected to the current mirror transistors is a gain transistor 126 and a gain transistor 124. A gate of gain transistor 124 is then coupled to a V.sub.REF which is typically about Vcc/2. Further, a gate of gain transistor 126 is shown interfacing with ROM core 100 via data bus 112 as described above. Coupled between transistor 122 and gain transistor 126 is amplified data output 114 that feeds to output buffer 108 where appropriate current amplification is performed.
FIG. 1C shows a conventional voltage response of data bus 112 with respect to time during an amplification operation by sense amplifier 106. As shown, data bus 112 initially starts at an approximate rail voltage (i.e., Vcc) of about 3.3 volts. As an example, when a memory location is addressed within ROM core 100 at a time t.sub.0, the voltage level on data bus 112 begins to decline over time due to current pull on data bus 112. As shown, the voltage level on data bus 112 continues to decline past a point 117 at time t.sub.1 (i.e., when data bus 112 intersects V.sub.REF) until a point 115 at time t.sub.2 is reached. Once time t.sub.2 is reached at a voltage difference "AEV" between V.sub.REF and data bus 112, sense amplifier 106 is triggered to a "HI" state and produces amplified data to output buffer 108 via amplified data output 114.
In general, if a AEV of about 50 mV is desired, sense amplifier 106 generally has to produce a gain of about 60 to produce about a 3 volt voltage swing at the output. Accordingly, by increasing the gain of sense amplifier 106, designers have been able to increase the speed at which sense amplifier 106 switches. Unfortunately, typical sense amplifiers are optimized for speed while ignoring the consequential increased levels of power consumption during memory accessing operations.
Generally the above described conventional ROM architecture works well for most applications in which low power consumption is not of any particular concern. However, in applications where low power consumption is needed, the high power consuming response of sense amplifier 106 may not be acceptable. Accordingly, sense amplifier 106 is not well suited for use in portable electronic devices that critically depend on a battery's limited useful life. As an example, many modern hand-held portable electronics devices such as laptop computers, pen-based computers and cellular phones, are many times rendered useless when memory accessing operations drain the electronic devices's battery.
In view of the foregoing, there is a needed for methods and apparatuses for providing low power consuming amplifiers used for memory accessing operations. In addition, there is a need for methods and apparatuses for efficiently powering down circuit devices within a sense amplifier once memory accessing amplification and data output latching is complete.